How a forge turns a prompt into a hardware package.

Six AI stages do the heavy reasoning in minutes; five deterministic stages finish in under a second. A full forge typically lands in about twenty minutes. Every stage records its own status, so the result is never a flat “done” — it is a set of artifacts, each labelled ready, estimated, degraded, or missing.

That honesty is the point. GravForge does not pretend an AI-generated board is fab-ready. It shows you the verification scorecard, the DRC/DFM findings, and the provenance of every part, then lets you download exactly the artifacts that are real.

1. 01DescribeIntent is parsed into a structured product brief.AI~15s
2. 02DecomposeThe brief is split into subsystems.AI~36s
3. 03SpecifyPer-subsystem specs and a power budget are derived.AI~4 min
4. 04BOMA parts list is assembled with provenance flags (verified / unverified / fallback).AI~4 min
5. 05FirmwareA PlatformIO scaffold plus drivers is generated.AI~4 min
6. 06AssembleA build guide and test procedures are written.AI~4 min
7. 07SchematicThe netlist is captured as a KiCad 8 schematic.Deterministic<1s
8. 08Validate14 electrical design rules run against the design.Deterministic<1s
9. 09PCB layoutPlacement, routing, and DRC produce an alpha board.Deterministic<1s
10. 10MechanicalAn OpenSCAD enclosure is generated from the board envelope.Deterministic<1s
11. 11CAD exportGerbers, drill, and BOM/POS CSVs are written.Deterministic<1s

Timings are typical averages from real forges, not best-case marketing numbers.

Every forge is checked, not just generated. The scorecard distils the scattered validation, routing, BOM, firmware, and manufacturing signals into five axes. Each axis is derived only from a field that actually exists on the result — when the data is absent, the axis reports N/A rather than a fabricated green check.

The overall verdict rolls up honestly: any fail makes the forge BLOCKED; any warning makes it REVIEW REQUIRED; only a clean, applicable pass is VERIFIED. The firmware axis is a structural buildability check, not a compile.

When a board passes its gates, GravForge assembles a single JLCPCB-uploadable ZIP: seven Gerber layers, an Excellon drill file, a BOM CSV, a pick-and-place (POS) CSV, and a README. It is built fresh on every download so it always reflects the latest design state.

The gate is strict. If routing quality is blocked (error-level DRC findings), the bundle is refused outright — both in the UI and at the API — so you can never download a bundle that a fab would reject. Boards with estimated or degraded routing still bundle, but the UI tones them amber for review first.

• Component selection. Parts come from an LLM-grown database that is not yet a verified parts catalogue — every line carries a provenance flag, and unverified parts are labelled as such.
• PCB layout is alpha. Placement and routing are usable for inspection and quoting, but a human should review DRC/DFM findings before ordering.
• Firmware buildability is structural, not compiled. The scorecard confirms files and a build config exist; it does not run the toolchain.
• The enclosure STL is only emitted for simple box geometries. Anything more complex stays as editable OpenSCAD source.

Downloads only appear once a project is saved, and only for artifacts that actually produced bytes. A missing or blocked artifact shows a disabled state rather than a link that 404s.